Search - fpga sdram

[VHDL-FPGA-Verilog] sdram_vhd

Description: FPGA设计的SDRAM控制器，有仿真代码，已通过验证-FPGA Design of SDRAM controller, there is simulation code has been validated
Platform: | Size: 2186240 | Author: yuhl | Hits:

[VHDL-FPGA-Verilog] 1189152740

Description: DDR2 SDRAM 控制器的FPGA实现-DDR2 SDRAM controller FPGA to achieve
Platform: | Size: 84992 | Author: 白皓 | Hits:

[VHDL-FPGA-Verilog] sdramled

Description: alter FPGA，包含sdram的nios系统开发实验完整工程文件-nios develop based nios IDE6.0，system involved an sdram
Platform: | Size: 1414144 | Author: 吴波 | Hits:

[VHDL-FPGA-Verilog] VerilogfoFPGAbasedSDRAMController

Description: 使用Verilog实现基于FPGA的SDRAM控制器-The use of Verilog for FPGA-based SDRAM Controller
Platform: | Size: 1680384 | Author: he | Hits:

Description: 对vga接口做了详细的介绍，并且有一 ·三段式Verilog的IDE程序，但只有DMA ·电子密码锁，基于fpga实现，密码正 ·IIR、FIR、FFT各模块程序设计例程， ·基于逻辑工具的以太网开发，基于逻 ·自己写的一个测温元件（ds18b20）的 ·光纤通信中的SDH数据帧解析及提取的 ·VHDL Programming by Example（McGr ·这是CAN总线控制器的IP核，源码是由 ·FPGA设计的SDRAM控制器，有仿真代码 ·xilinx fpga 下的IDE控制器原代码, ·用verilog写的，基于查表法实现的LO ·精通verilog HDL语言编- up:in STD_LOGIC down:in STD_LOGIC run_stop:in STD_LOGIC wai_t: in std_logic_vector(2 downto 0) lift:in std_logic_vector(2 downto 0) ladd: out std_logic_vector(1 downto 0) ) end control
Platform: | Size: 18683904 | Author: liuzhou | Hits:

[VHDL-FPGA-Verilog] SDRAM_VerilogCode

Description: 基于FPGA的SDRAM控制器Verilog代码，开发环境为Quartus6.1，控制SDRAM实现对同一片地址先写后读。-FPGA-based SDRAM controller Verilog code, development environment for Quartus6.1, control of SDRAM to achieve the same address one after the first time to write.
Platform: | Size: 26624 | Author: 姜琰俊 | Hits:

[VHDL-FPGA-Verilog] cameralink

Description: 由于目前基于CameraLink接口的各种相机都不能直接显示，因此本文基于Xilinx公司的Spartan 3系列FPGAXC3S1000-6FG456I设计了一套实时显示系统，该系统可以在不通过系统机的情况下，完成对相机CameraLink信号的接收、缓存、读取并显示系统采用两片SDRAM作为帧缓存，将输入的CameraLink信号转换成帧频为75Hz，分辨率为1 024×768的XGA格式信号，并采用ADV7123JST芯片实现数模转换，将芯片输出的信号送到VGA接口，通过VGA显示器显示出来-As the CameraLink interface is currently based on a variety of cameras can not directly display, this article based on Xilinx' s Spartan 3 series FPGAXC3S1000-6FG456I designed a set of real-time display system, the system can be achieved without machine case through the system to complete the CameraLink cameras signal reception, cache, read and display systems use two SDRAM frame buffer as the input signals into the CameraLink frame rate of 75Hz, a resolution of 1 024 × 768 for XGA format signal, and using ADV7123JST chip digital-analog conversion, the chip output signal to the VGA port, through the VGA display monitor
Platform: | Size: 13312 | Author: lilei | Hits:

[VHDL-FPGA-Verilog] mem_ctrl_latest.tar

Description: 存储器控制FPGA程序，包括ram，fifo，sdram，flash等。-FPGA memory control processes, including ram, fifo, sdram, flash and so on.
Platform: | Size: 331776 | Author: zhangsan | Hits:

[VHDL-FPGA-Verilog] my_sram

Description: 在sopc builder 中填加SDRAM(IS61LV25616AL),能够直接被系统识别。-Sopc builder filled in Canada in the SDRAM (IS61LV25616AL), the system can be directly identified.
Platform: | Size: 20480 | Author: desd | Hits:

[Software Engineering] median

Description: 中值滤波的实现，该代码使用的是verilog 语言 module median(clk,reset,load,din,mult,dout,over,a3,b3,c3,a2,b2,c2,a1,b1,c1)-Median filter implementation, the code using verilog language module median (clk, reset, load, din, mult, dout, over, a3, b3, c3, a2, b2, c2, a1, b1, c1)
Platform: | Size: 2048 | Author: 刘文英 | Hits:

[VHDL-FPGA-Verilog] ddr_sdr_V1_1

Description: DDR控制器 - 用XILINX Virtex II FPGA实现 - 使用DDR MT46V16M16作为仿真模型 - 通用化-DR SDRAM Controller Core - has been designed for use in XILINX Virtex II FPGAs - works with DDR SDRAM Device MT46V16M16 without changes - may be easily adapted to any other DDR SDRAM device
Platform: | Size: 37888 | Author: jordanliang | Hits:

[VHDL-FPGA-Verilog] Verilog-DRAM

Description: fpga(veriloh hdl)编写的SDRAM程序说明 -fpga(veriloh hdl)SDRAM
Platform: | Size: 1680384 | Author: SHIGANG | Hits:

[VHDL-FPGA-Verilog] sdram_control.RAR

Description: 基于XILINX FPGA的SDRAM 控制器代码。VERILOG HDL代码编写-SDRAM CONTROLER
Platform: | Size: 3695616 | Author: bigchop ma | Hits:

[Software Engineering] TheResearchoftherealtimesignalprocessingofSARbased

Description: 3．完成系统的FPGA程序开发与调试，主要包括FFT，IFFT，CMUL和转置存储控制等模块，在此基础上，重点介绍了一种基于DDR SDRAM的行写行读高效转置存储算法，在采用该算法进行转置存储操作时，读写两端的速度相匹配，满足流水线操作要求，提高了整个系统的实时性。最后介绍了采用CORDIC算法实现复图像求模运算的方法，分析了算法的硬件实现结构，并给出了基于FPGA 的实现方法及仿真结果。-he FPGA s development and debugging are implemented,including FFT, IFFT, CMUL and C0ntrol of CTM．Based Oll this，Implementation of a high efficient corner turn memory arithmetic with writing and reading by row based on DDR SDRAM is introduced．When using CTM with this algorithm，me speed of reading and writing maItches and meets the requirement of pipelined operation．Finally a method of model implementation for complex image based on CORDIC algorithm is introduced．The algorithm’s hardware implementation structure is analysed, and implementation methodology and simulation results are given
Platform: | Size: 5155840 | Author: mabeibei | Hits:

[Other] sdram_normal

Description: sdram控制器，用于fpga中的sdram读写和刷新控制-sdram controler in FPGA
Platform: | Size: 2048 | Author: mingleicui | Hits:

[VHDL-FPGA-Verilog] sdram

Description: 用verilog语言编程实现的SDRAM模块，可用于配置在FPGA中-Verilog language programming with the SDRAM module, can be used to configure the FPGA,
Platform: | Size: 4096 | Author: 王羽翾 | Hits:

[Embeded-SCM Develop] 61EDA_D556

Description: FPGA中的SDRAM的设计，用VERILOG语言设计-fpga sdram
Platform: | Size: 5120 | Author: shang | Hits:

[VHDL-FPGA-Verilog] memtest

Description: 在数字系统中，一般存在多个芯片，利用不同的特点用于实现不同的功能，一般都包含CPU,FPGA,AD,DA,memory，ASSP（专用标准模块）,ASIC等。CPU用于进行智能控制，FPGA进行硬件算法处理和多设备接口，AD进行模数转换，DA进行数模转换，memory存储临时数据。因此，FPGA如何与其他芯片进行通讯是重要的设计内容。数据输入，数据输出，双向通讯，指令传递，地址管理，不同时钟的异步通讯问题等等都需要处理。最基本的MEMORY如SRAM(128KX8bbit静态存储器628128)涉及到其中的输入，输出，双向通讯，地址管理问题，具有很强的代表性。在同步数字系统中更大量用到FIFO,SDRAM等等。其中FIFO使用方便简单，用处很广。在QUARTUSII软件库中，就有各种FPGA片内MEMORY供使用。但是FPGA的片内MEMORY容量太有限，因此外部MEMORY也是经常需要的。因此，本程序让大家学习控制芯片内外的MEMORY,为与其他智能设备的通讯学习打下基础。-In the digital system, generally there are several chips, the use of different features used to implement different functions, generally includes CPU, FPGA, AD, DA, memory, ASSP (application specific standard module), ASIC and so on. CPU is used for intelligent control, FPGA hardware algorithm processing and multi-device interface, AD to ADC, DA for digital-analog conversion, memory to store temporary data. Therefore, FPGA how to communicate with other chips are important design elements. Data input, data output, two-way communication, instruction delivery, address management, different clock asynchronous communication problems, and so have to deal with. If the most basic MEMORY SRAM (128KX8bbit static memory 628 128) which involved the input, output, bi-directional communication, address management issues, with strong representation. In synchronous digital systems a lot more use FIFO, SDRAM, etc.. One simple and easy to use FIFO, use very broad. In QUARTUSII software library, there ar
Platform: | Size: 223232 | Author: 平凡 | Hits:

[Other] FTOD_SDRAM10.3.18

Description: FPGA与DSP数据接口转换时序，简单实用的，SDRAM时序读写数据。-FPGA and DSP data interface conversion timing, simple and practical, SDRAM read and write data timing.
Platform: | Size: 13487104 | Author: 郝金 | Hits:

[VHDL-FPGA-Verilog] a12

Description: FPGA读写SDRAM的VHDL程序(已经测试过)-FPGA SDRAM read and write the VHDL program (already tested)
Platform: | Size: 6144 | Author: 刘志杰 | Hits:

« 1 2 3 4 5 67 8 9 10 11 ... 15 »

Category

Source Code

Web/Internet

Develop Tools

Document

Other

Search in results

OS

Platform

Language

File Type

Search list